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Semiconductor
S3882P
Current Mode PWM Controller
Descriptions
The S3882 is fixed PWM controller for Off-line and DC-DC converter applications. The internal circuits include UVLO, low start up current circuit, temperature compensated reference, high gain error amplifier, current sensing comparator, and high current totempole output for driving a power MOSFET. Also S3882 provide low start up current below 0.3mA and short shutdown delay Time typical 100nsec. S3882 have UVLO threshold of 16V(on) and 10V(off). .
Features
* Low start up current < 0.3mA * Operating range up to 500KHz * Cycle by cycle current limiting * Under Voltage Lock Out with hysteresis * Short shutdown delay time ; typical 100nsec * High current totempole output * Output swing limiting : 22V
Ordering Information
Type NO. S3882P Marking S3882P Package Code DIP-8
Outline Dimensions
unit :
mm
PIN Connections
1. Output / Compensation 2. Voltage feedback. Input 3. Current sense Input 4. Rt/Ct 5. GND 6. Output 7. Vcc 8. Vref
KSI-L008-000
1
S3882P
Absolute Maximum Ratings
Characteristic
Supply Voltage Output Current Analog Inputs Error Amp. Output Sink current Power Dissipation
Ta=25C
Symbol
Vcc Io Vi(ana) Isink(EA) Pd
Ratings
28 1 -0.3 to 6.3 10 1
Unit
V A V mA W
Electrical Characteristics
(Vcc=15V, Rt=10Kohm,Ct=3.3nF, Ta=0 to 70, Unless otherwise specified)
Characteristic
1. Reference Section
Output Voltage Line Regulation Load Regulation Output Short Current
Symbol
Vref Vref Vref Isc fOSC f /V VOSC Idischarge
Test Condition
Tj=25, Io=1mA
12V VCC 25V 1mA IO 20mA
Min.
4.91 -180 47 1.4 7.8
Typ. Max.
5.00 6 6 -100 52 0.2 1.7 8.3 5.09 20 25 57 1.0 1.8 8.8
Unit
V mV mV mA KHz % V mA
Ta=25C
Tj=25 12V VCC 25V Vpin4, peak to peak Tj=25C, Pin4=2V
2. Oscillator Section
Initial Accuracy Voltage Stability Oscillator Voltage Discharge Current
3. Error Amp Section
Input Voltage Input Bias Current Open Loop Voltage Gain Unity Gain Bandwidth PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage V2 Ib AVO1 GBW PSRR1 ISINK ISOURCE VOH VOL VPIN1=2.5V 2V VO 4V Tj=25C VCC=12V to 25V VPIN2=2.7V, VPIN1=1.1V VPIN2=2.3V, VPIN1=5V Vpin2=2.3V, R1=15 to GN VPIN2=2.3V, R1=15 to PIN8 5 2.42 -2.0 65 0.7 60 2 2.50 -0.3 90 1 70 6 -0.8 6 0.8 2.58 -0.5 1.1 V MHz mA mA V V
4. Current Sense Section
Gain Maximum Input Signal PSRR Input Bias Current Delay to Output GV Vi(MaX) PSRR2 I
bias
VPIN 1=5V 12V VCC 25V VPIN 3=0V to 2V
2.85 0.9 -10 -
3.0 1.0 70 -2 100
3.15 1.1 200
V/V V nS
Td
KSI-L008-000
2
S3882P
Electrical Characteristics(continued)
(Vcc=15V, Rt=10Kohm, Ct=3.3nF, Ta=0to 70, Unless otherwise specified)
Characteristic
5. Output Section
Output Low Level1 Output Low Level2 Output High Level1 Output High Level2 Rise Time Fall Time Out Volt. Swing Limit
Symbol
VOL1 VOL2 VOH1 VOH2 tr tf Volim Vth VtL Dmax Dmin Ist ICC VZ
Test Condition
Isink=20mA Isink=200mA Isource=20mA Isource=200mA Tj=25C, C1=1nF Tj=25C, C1=1nF
Vcc=27V, C1=1nF After turn on
Min.
13.0 12.0 -
Typ. Max.
0.1 1.5 13.5 13.5 40 40 22 0.4 2.0 100 100 -
Unit
V V V V nS nS V
6. Under Voltage Lockout Section
Start Threshold Min. Operating Voltage 15 9 16 10 17 11 V V
7.PWM Section
Maximum Duty Cycle Minimum Duty Cycle 94 96 100 0 % %
8.Total Standby Section
Start-Up Current Operating Supply Current VCC Zener Voltage 0.2 11 29 0.4 17 mA mA V
Vpin2=Vpin3=0V
ICC=25mA
NOTE: Adjust Vcc above the the start threshold before setting at 15V
Block Diagram
7 29V 5V V ref Set/ Re s e t
Vcc
Vref
8
5 UV LO
GND
In t e r n al Bi as
LO G IC
PWR Vc
1/2 V r e f Er r or Amp C.S Comp 1/3 1V PWM LATCH 7
Vfb
2
+ -
R
22V 6
Output
Com 1 C.S
3
S
PWR GND
5
Rt/Ct
4 Os c i l l at or
KSI-L008-000
3
S3882P
Information in Using IC 1. Under voltage Lockout
To prevent erratic output behavior which activating
V cc 7 O N /O F F C O M M A N D T O R ES ET O F IC
the power switch with extraneous leakage currents, during under voltage lockout. Output(pin6) should be shunted to ground with a bleeder resister.
V o n -16V V o f f -10V
Icc
The Vcc comparator upper and lower threshold are 16V/10V. The large hysteresis and low start up currents makes it ideally suited in off-line converter
<17mA
application where efficient bootstrap start-up techniques are required.
<1mA 10V 16V V cc
2. Oscillator Waveforms and Maximum Duty Cycle
LARGE Rt SMALL Ct
8 Rt 4 Ct 5
The oscillator frequency is programmed by the values
Vpin4
selected for the timing components Rt and Ct. Ct is charged from 5V, Vref, through resistor Rt to approximately 2.8V and discharged to 1.2V by an internal current sink. During the discharge of Ct, the oscillator generates an internal blanking pulse and the center input NOR gate high. This makes output to be in a low state and control the amount of output dead time.
INTERNAL CLOCK SMALL Rt LARGE Ct
Vpin4
INTERNAL CLOCK
3. Error AMP Configuration
2.50V
Error amp output(Pin1) is provided for external loop
+ 0.5mA
compensation and error amp can source or sink up to 0.5mA. The non-inverting input is internally biased at 2.5V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input(pin2).
V in
Zt
COMP
2
-
Zf
1
KSI-L008-000
4
S3882P
4. Current Sense Circuit
ER R O R A MP 2R I R R (V p i n 1 - 2V b e ) Ip e a k = 3R x R s R 3 C Rs 5 1 CO MP CUR R E NT S ENS E G ND IV CUR R ENT S E NS E C O MP A R A T O R
A normal operating conditions occurs when the power supply output is overloaded or if output voltage to 1.0V Therefore the maximum peak switch current is lpk(max)=1.0V/Rs, and under the normal operating conditions the peak inductor current controlled by the voltage at pin1.
5. Shutdown Techniques
4.7K 8 V
RE F
1
CO MP
Shutdown of the S3882 can be accomplished by two methods; either raise pin3 above 1V or pull
3 4.7K S HUT DO W N T O CUR R E NT S E NS E R ES I S T O R 5.00
ISEN S E
S HUT DO W N
pin1 below a voltage two diodes drops above ground. Either causes the output of the PWM method comparator to be high (refer to
block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which turn off, allowing the SCR to reset.
KSI-L008-000
5
S3882P
6. Open Loop Test
V REF 2N2222 4.7K 100K 1 COMP 2 ISENSE ADJUST 3 4 V in V REF 5 V cc OUTPUT 6 7 8 0.1uF 0.1uF 1K/1W OUTPUT RT V cc
ERROR 1K AMP ADJUST 4.7K
S3882
ISENSE RT/CT
GND
GROUND
High peak currents associated with capacitive leads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to Pin5 in a single point ground. The transistor and 5 potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Pin 3.
7.Slope Compensation
V
0.1u F
RE F
A fraction of the oscillator ramp can be resistively
RT
8
summed with the current sense signal to provide slope compensation for converters requiring duty cycle over 50%. Note that capacitor C, forms a
R1 R2 I SEN SE
R T /C T
4
CT
filter with R2 to suppress the leading edge switch spikes.
I SEN SE
3 C R SEN SE
KSI-L008-000
6
S3882P
Electrical Characteristic Curves
OUTPUT DEAD-TIME vs. OSCILLATOR FREQUENCY
100 %DT PERCENT OUTPUT DEAD-TIME 50 20 10 5.0 200pF 2.0 1.0 10K 20K 50K 100K 200K 100pF V c c =15V Ta = 25o C 5.0n F
R T TIMING RESISTOR (K) 80 50 500pF 5.0n F 100pF
TIMING RESISTOR vs. OSCILLATOR FREQUENCY
2.0n F 1.0n F
20 8.0 5.0 2.0
Ct =10n F
500pF
200pF
V c c =15V Ta = 25o C 20K
2.0n F 1.0n F CT=10n F 50K 100K 200K 500K 1.0M
500K 1.0M
0.8 10K
fOSC OS CILLATOR FREQUENCY (KHz )
fOSC OS CILLATOR FREQUENCY (KHz )
Error Amplifier Open-Loop Frequency Response
SATURATION VOLTAGE (V)
VOLTAGE GAIN (dB) 80 60 40 20 AV 0 -180 -90 -135 0 PHASE (
o
Output Saturation Characteristics
4 Vcc=15V Ta = 25o C 3 Ta=-55o C
-45
2
)
1
SOURCE SAT(Vcc-VOH) SINK SAT(VOL)
0
10 100 1K 10K 100K 1M 10M
0.1
0.2
0.3 0.4 0.5 0.7
1
2
3
4
5
7
10
FREQUENCY (Hz)
OUTPUT CURRENT SOURCE OR SINK (A)
KSI-L008-000
7

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